This application is based on applications Nos. 10-021089 and 10-364143 filed in Japan, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a design aiding apparatus for designing a circuit board with a low noise level, a design aiding method, and a storage medium storing a design aiding program.
2. Description of the Prior Art
With the development of multilayer printed circuit boards, circuit boards that include not only signal wiring surfaces but also solid conductor surfaces (planes), such as a 0-volt ground plane, a 5-volt power plane and a 12-volt power plane, have increasingly been used in recent years.
A CAD apparatus for such multilayer circuit boards is disclosed in Japanese Laid-Open Patent Application 9-26979. In this CAD apparatus, the geometry of each subplane of a power plane is generated based on data inputted by a designer for specifying a voltage level of each component and an approximate boundary line between each two component groups. More specifically, once the designer has inputted a voltage level of each component and roughly specified a boundary line between each two component groups which have different voltage levels, the CAD apparatus detects intersection points between the specified boundary lines and the peripheral lines of a board, forms areas (closed loops) which each enclose a component group, and calculates the geometry of a subplane (expressed by a coordinate string showing a continuous line created by inwardly offsetting a closed loop) for each closed loop. Thus, only by specifying voltage levels of components and rough boundary lines between component groups, the designer can design the geometry of each subplane which differs in voltage level. In addition, even when components are randomly placed irrespective of their voltage levels, the complex geometries of subplanes can be obtained by generating closed loops along boundary lines between component groups.
In a circuit board containing high-speed signal lines, a high-speed signal normally takes a feedback path of the lowest impedance. In the case of a multilayer circuit board, a signal of a high-speed signal line routed on a signal layer mostly takes a feedback path formed by projecting the signal line onto a plane nearest to the signal layer. This technique is described in detail in Mark I. Montrose (1996) Printed Circuit Board Design Techniques for EMC Compliance, IEEE No. PC5595, and Howard W. Johnson and Martin Graham (1993) High-Speed Digital Design: A Handbook of Black Magic, PTR Prentice-Hall.
For suppressing undesired electromagnetic waves in designing a high-speed signal rigid circuit board, a printed circuit board designing method is disclosed in Japanese Laid-Open Patent Application 6-203102, while a printed circuit board, a printed circuit board designing method and a wiring pattern generating apparatus for a printed circuit board are disclosed in Japanese Laid-Open Patent Application 9-186465.
In the printed circuit board designing method disclosed in Japanese Laid-Open Patent Application 6-203102, each component block is placed so that high-frequency digital signal lines can be linearly routed between each two component block either in the X or Y direction on a signal layer, and the appearance of cutlines orthogonal to the direction of the signal lines is prohibited in an area formed by projecting the signal lines onto a power/ground layer nearest to the signal layer. By doing so, radiated electromagnetic noise can be reduced.
In the printed circuit board designing method disclosed in Japanese Laid-Open Patent Application 9-186465, two signal patterns are grouped as one in a printed circuit board composed of a signal layer, a power layer and a ground layer. Vias on two signal patterns of the same group are placed closely so that the signal patterns are insulated from each other, while vias on two signal patterns of different groups are placed with a space larger than the sum of the clearance diameter and the signal pattern width. By setting a clearance around each via hole in the above arrangement, a feedback path of a signal pattern is routed in the vicinity of an area formed by projecting the signal pattern onto the power/ground layer, with it being possible to reduce radiated electromagnetic noise caused by the signal pattern and a largely detoured feedback path.
However, the multilayer circuit board CAD apparatus of Japanese Laid-Open Patent Application 9-26979 lacks efficiency on the ground that the designer has to manually input boundary lines between component groups of different voltage levels. Besides, to connect components of a high-speed circuit group to one subplane adversely affects other component groups.
Although the printed circuit board designing method of Japanese Laid-Open Patent Application 6-203102 is effective in suppressing radiated electromagnetic noise, it is necessary to place component blocks in consideration of routing directions of high-speed signal lines and to route feedback paths in areas parallel to signal lines in consideration of directions of the signal lines and positions of via holes. Thus, this method has difficulties in designing a circuit board under the above constraints.
Also, the printed circuit board designing method of Japanese Laid-Open Patent Application 9-186465 fails to sufficiently suppress electromagnetic noise, since a signal of a signal line still takes an alternative path to avoid non-conductor areas around via holes directly below the signal line.
In view of the above problems, the present invention aims to provide a design aiding apparatus, a design aiding method and a storage medium storing a design aiding program that enable efficient design of a circuit board while suppressing electromagnetic noise and adverse effect caused by high-speed circuit blocks on other circuit blocks, without concern for design restrictions, such as placement of component blocks in consideration of directions of high-speed signal lines and routing of feedback paths in consideration of directions of signal lines and positions of via holes.
To fulfill the above object, the present invention is a design aiding apparatus for aiding placement of any of components, conductors and vias in a multilayer circuit board which includes at least one signal layer and at least one layer that is one of a power layer and a ground layer, the design aiding apparatus including: a routing path area generating unit for generating a routing path area on at least one signal layer or at least one layer that is one of a power layer and a ground layer, the routing path area partly including one of a signal line routed on a signal layer and a feedback path of a current which flows over a signal line routed on a signal layer; and a position calculating unit for calculating, based on the generated routing path area, one of a position at which any of components, conductors and vias is to be placed and a position at which any of components, conductors and vias is prohibited to be placed, to minimize an area enclosed by a loop formed by a current which flows over a signal line and a feedback path corresponding to the signal line.
With this construction, an area enclosed by a loop formed by a current that flows over a signal line and a feedback path corresponding to the signal line can be minimized by determining where any of components, conductors and vias is to be placed or where any of components, conductors and vias is prohibited to be placed, based on a routing path area set on a signal, power, or ground layer. Accordingly, a circuit board that has a low noise level can be designed with efficiency.
The above object can also be fulfilled by a design aiding apparatus for aiding placement of vias in a multilayer circuit board which includes at least one layer that is one of a ground layer and a power layer and at least one signal layer on which at least one conductor that interconnects terminals of respective components is placed, the design aiding apparatus including: an interconnection storing unit for storing at least one interconnection identifier identifying an interconnection of terminals of respective components; a conductor storing unit for storing at least one combination of a conductor placement area and a layer identifier for each interconnection identifier identifying an interconnection of terminals of respective components, the conductor placement area showing an area occupied by a conductor which one of totally and partially interconnects the terminals of the respective components, and the layer identifier identifying a layer on which the conductor is placed; an interconnection identifier selecting unit for selecting an interconnection identifier; a conductor detecting unit for detecting at least one combination of a conductor placement area and a layer identifier corresponding to the selected interconnection identifier from the conductor storing unit, a layer identified by the detected layer identifier being set as a conductor placement layer; a power/ground layer detecting unit for detecting a layer, among power layers and ground layers included in the multilayer circuit board, that is nearest to the conductor placement layer; and a prohibition area generating unit for generating a placement prohibition area within which placement of vias is prohibited, on the detected layer, wherein the placement prohibition area is an area formed by projecting an area, which encloses the detected conductor placement area by a predetermined gap, onto the detected layer.
With this construction, placement of vias is prohibited in a placement prohibition area on a plane nearest to a signal layer on which a signal line of a detected net is routed, in order to prevent non-conductor areas around via holes from being created in a feedback path area for the signal line. Accordingly, a feedback path of a current that flows over the signal line can be secured, with it being possible to efficiently design a circuit board with a low noise level.
The above object can also be fulfilled by a design aiding apparatus for aiding placement of vias in a multilayer circuit board which includes at least one signal layer, at least one power layer and at least one ground layer, the design aiding apparatus including: a component storing unit for storing at least one component identifier identifying a component placed on a signal layer and storing at least one capacitor element identifier identifying a capacitor element placed on a signal layer; a component selecting unit for selecting a component identifier; and a capacitor element selecting unit for selecting a capacitor element identifier identifying a capacitor element that is connected to a pair of power and ground layers to which a component identified by the selected component identifier is connected, that has a predetermined capacitance, and that is placed nearest to the component on a signal layer on which the component is placed.
Here, the design aiding apparatus may further include a rectangle area setting unit for setting an area, formed by projecting a rectangle area whose diagonal vertices correspond to a placement position of the capacitor element and a placement position of the component on the signal layer onto a layer that is nearer to the signal layer among the pair of power and ground layers to which the component is connected, as a clearance radius change area.
Here, a plurality of layers may be connected by vias whose clearances each have a predetermined radius, each clearance being a circular area centering on a via, where placement of another via is prohibited, wherein the design aiding apparatus further includes a clearance radius changing unit for changing the predetermined radius of a clearance of each via which passes through the set clearance radius change area, to a different value.
With this construction, overlapping of non-conductor areas around adjacent via holes is avoided in a specific area on a plane nearest to a signal layer on which a signal line of a detected net is routed, so that a feedback path of a current that flows over the signal line can be secured. Accordingly, a circuit board with a low noise level can efficiently be designed.
The above object can also be fulfilled by a design aiding apparatus for aiding placement of conductors in a multilayer circuit board in which at least one signal layer and at least one layer that is one of a power layer and a ground layer are included in a predetermined order, the design aiding apparatus including: an interconnection storing unit for storing at least one interconnection identifier identifying an interconnection of terminals of respective components; a layer type storing unit for storing a combination of a layer identifier and a layer type for each layer in the multilayer circuit board in the predetermined order, the layer identifier identifying a layer, and the layer type showing whether the layer identified by the layer identifier is a signal layer, a power layer, or a ground layer; an interconnection identifier selecting unit for selecting an interconnection identifier identifying an interconnection of terminals of respective two components; a power/ground layer detecting unit for detecting at least one layer to which the two components are connected among power layers and ground layers included in the multilayer circuit board, and detecting a layer identifier that identifies the detected layer from the layer type storing unit; a signal layer detecting unit for detecting at least one signal layer on which the two components are placed and detecting a layer identifier identifying the detected signal layer; a priority determining unit for assigning priorities to the signal layers included in the multilayer circuit board, based on combinations of layer identifiers and layer types stored in the layer type storing unit in the predetermined order, the layer identifier detected by the power/ground layer detecting unit, and the layer identifier detected by the signal layer detecting unit; a routing layer determining unit for determining at least one signal layer on which a conductor will be placed to interconnect the terminals of the respective two components, based on the priorities assigned by the priority determining unit; and a routing unit for calculating a placement area of the conductor on the determined signal layer.
With this construction, a signal line of a detected net is routed on a signal layer nearest to a power/ground plane, so that an area enclosed by a loop of a current that flows over the signal line can be minimized. Thus, it is possible to efficiently design a circuit board with a low noise level.
The above object can also be fulfilled by a design aiding apparatus for aiding placement of conductors in a multilayer circuit board in which at least one signal layer and at least one layer that is one of a power layer and a ground layer are included in a predetermined order, the design aiding apparatus including: an interconnection storing unit for storing at least one interconnection identifier identifying an interconnection of terminals of respective components; a conductor storing unit for storing at least one layer identifier for each interconnection identifier identifying an interconnection of terminals of respective components, the layer identifier identifying a signal layer one which a conductor which one of totally and partially interconnects the terminals of the respective components is placed; an interconnection identifier selecting unit for selecting an interconnection identifier identifying an interconnection of terminals of respective two components; a conductor detecting unit for detecting at least one layer identifier corresponding to the selected interconnection identifier from the conductor storing unit, a signal layer identified by the detected layer identifier being set as a conductor placement layer; and a routing layer judging unit for judging whether the conductor placement layer is a predetermined signal layer.
Here, the routing layer judging unit may include: a layer type storing unit for storing a combination of a layer identifier and a layer type for each layer in the multilayer circuit board according to the predetermined order, the layer identifier identifying a layer, and the layer type showing whether the layer identified by the layer identifier is a signal layer, a power layer, or a ground layer; a power/ground layer detecting unit for detecting at least one layer to which the two components are connected among the power layers and ground layers included in the multilayer circuit board and detecting a layer identifier that identifies the detected layer from the layer type storing unit; a signal layer detecting unit for detecting at least one signal layer on which the two components are placed and detecting a layer identifier identifying the detected signal layer from the layer type storing unit; a priority determining unit for assigning priorities to the signal layers included in the multilayer circuit board, based on the combination of the layer identifier and the layer type for each layer in the layer type storing unit, the layer identifier detected by the power/ground layer detecting unit, and the layer identifier detected by the signal layer detecting unit; and a priority judging unit for judging whether there is a signal layer whose priority is higher than a priority assigned to the conductor placement layer, based on the priorities assigned by the priority determining unit.
Here, the conductor storing unit may further store, for each interconnection identifier identifying an interconnection of terminals of respective components, at least one conductor placement area showing an area occupied by a conductor which one of totally and partially interconnects the terminals of the respective components, wherein the design aiding apparatus further includes a conductor moving unit for deleting, when the priority judging unit judges that there is the signal layer of a higher priority than the conductor placement layer, the layer identifier and a conductor placement area corresponding to the selected interconnection identifier from the conductor storing unit, calculating a new conductor placement area on the signal layer of the higher priority to place a conductor which interconnects the terminals of the respective two components, and writing a combination of the new conductor placement area and a layer identifier identifying the signal layer of the higher priority into the conductor storing unit.
With this construction, a signal line of a detected net is checked whether it has been routed on a signal layer nearest to a power/ground plane, with it being possible to design a circuit board that has a low noise level.
The above object can also be fulfilled by a design aiding apparatus for aiding placement of any of conductors and vias in a multilayer circuit board which includes at least one signal layer, at least one power layer and at least one ground layer, the design aiding apparatus including: an interconnection storing unit for storing at least one interconnection identifier identifying an interconnection of terminals of respective components; a component storing unit for storing a combination of a component identifier, a layer identifier, a component placement position and a component type for each component placed in the multilayer circuit board, the component identifier identifying a component, the layer identifier identifying a signal layer on which the component is placed, the component placement position showing a placement position of the component on the signal layer, and the component type showing a type of the component; an interconnection identifier selecting unit for selecting an interconnection identifier which identifies an interconnection between a terminal of a first component and a terminal of a second component; a component detecting unit for detecting a component identifier identifying the first component and a component identifier identifying the second component from the component storing unit; a component placement layer judging unit for retrieving a layer identifier corresponding to the component identifier of the first component and a layer identifier corresponding to the component identifier of the second component from the component storing unit, setting a signal layer identified by the layer identifier retrieved for the first component as a first signal layer and a signal layer identified by the layer identifier retrieved for the second component as a second signal layer, and judging whether the first signal layer and the second signal layer are same; a rectangle area generating unit for generating a rectangle area on the first signal layer when the component placement layer judging unit judges that the first signal layer and the second signal layer are different, wherein diagonal vertices of the rectangle area correspond to a placement position of the terminal of the first component and a point formed by projecting a placement position of the terminal of the second component onto the first signal layer; a capacitor element judging unit for searching the component storing unit for a component identifier identifying a component that is connected to a pair of power and ground layers to which the first component and the second component are connected, that is a capacitor element, and that is placed within the generated rectangle area; a via placing unit for calculating a predetermined position on the first signal layer as a via placement position when the component identifier is found by the capacitor element judging unit; and a routing unit for calculating a conductor placement area on the first signal layer to place a conductor which connects the terminal of the first component and the calculated via placement position, and calculating a conductor placement area on the second signal layer to place a conductor which connects the terminal of the second component and a point formed by projecting the calculated via placement position onto the second signal layer.
With this construction, when a via that connects two conductors placed for a detected net passes through power and ground planes, the via is placed near a capacitor element which forms a part of a feedback path of a current that flows over the detected net. Accordingly, an area enclosed by a loop of the current can be minimized, with it being possible to design a circuit board while reducing noise.
The above object can also be fulfilled by a design aiding apparatus for aiding placement of any of components, conductors and vias in a multilayer circuit board which includes at least one signal layer, at least one power layer and at least one ground layer in a predetermined order, the design aiding apparatus including: an interconnection storing unit for storing at least one interconnection identifier identifying an interconnection of terminals of respective components; a capacitor element storing unit for storing a placement position of each capacitor element, among capacitor elements placed on any of the signal layers, that is connected to a pair of power and ground layers; a layer type storing unit for storing a combination of a layer identifier and a layer type for each layer in the multilayer circuit board according to the predetermined order, the layer identifier identifying a layer, and the layer type showing whether the layer identified by the layer identifier is a signal layer, a power layer, or a ground layer; a conductor storing unit for storing at least one combination of a conductor placement area and a layer identifier for each interconnection identifier identifying an interconnection of terminals of respective components, the conductor placement area showing an area occupied by a conductor that one of totally and partially interconnects the terminals of the respective components, and the layer identifier identifying a signal layer on which the conductor is placed; a via storing unit for storing a via placement position of each via that connects a plurality of layers; an interconnection identifier selecting unit for selecting an interconnection identifier identifying an interconnection between a terminal of a first component and a terminal of a second component; a conductor detecting unit for detecting at least one combination of a conductor placement area and a layer identifier corresponding to the selected interconnection identifier from the conductor storing unit; a via judging unit for searching the via storing unit for a via whose via placement position is within any of the detected conductor placement areas; a nearest plane judging unit for judging, when the via judging unit finds the via and when the conductor detecting unit detects two layer identifiers which respectively identify a first signal layer on which a first conductor is placed and a second signal layer on which a second conductor is placed, whether among the power layers and the ground layers included in the multilayer circuit board, a first layer that is nearest to the first signal layer is different from a second layer that is nearest to the second signal layer, based on combinations of layer identifiers and layer types stored in the layer type storing unit in the predetermined order; and a capacitor placement judging unit for searching, when the nearest plane judging unit judges that the first layer and the second layer are different, the capacitor element storing unit for a capacitor element that is connected to the first layer and the second layer and that is placed within a predetermined distance from the via placement position of the via found by the via judging unit.
Here, the via judging unit may include: a grouping unit for grouping signal layers to which a same layer, among the power layers and the ground layers included in the multilayer circuit board, is nearest, based on the combinations of the layer identifiers and the layer types stored in the layer type storing unit in the predetermined order; and a sub via judging unit for reading a via placement position of each via that connects two signal layers belonging to different groups, and judging whether the read via placement position is within any of the detected conductor placement areas.
Here, the design aiding apparatus may further include: a rectangle area generating unit for generating a rectangle area on the first signal layer when no capacitor element is found by the capacitor placement judging unit, wherein diagonal vertices of the rectangle area correspond to a placement position of the terminal of the first component and a point formed by projecting a placement position of the terminal of the second component onto the first signal layer; and a rectangle area capacitor placement judging unit for searching the capacitor element storing unit for a capacitor element that is connected to the first layer and the second layer and that is placed within the generated rectangle area.
With this construction, when a via that connects two conductors placed for a detected net passes through power and ground planes, it is checked whether a capacitor element that can be a part of a feedback path of a current flowing over the detected net exists in a rectangle area whose diagonal vertices correspond to a position of a component terminal at one end of the net and a point formed by projecting a position of a component terminal at the other end of the net onto a signal layer. By doing so, a circuit board with a low noise level can be designed with efficiency.
The above object can also be fulfilled by a design aiding apparatus for aiding placement of conductors in a multilayer circuit board which includes at least one signal layer, at least one power layer and at least one ground layer, the design aiding apparatus including: a component detecting unit for detecting components which are to be interconnected by a predetermined signal line on a signal layer; a plane detecting unit for detecting a position of each layer, among the power layers and the ground layers, to which the components are connected and detecting a shape of a conductor area of each layer to which the components are connected; a routing area setting unit for setting an area formed by projecting an area defined by the detected position and the detected shape onto the signal layer, as a routing area for the predetermined signal line; and a routing unit for calculating a conductor placement area within the routing area to place each conductor to interconnect the components.
With this construction, a feedback path of a high frequency signal that flows over a predetermined signal line is secured on a power/ground plane, so that a circuit board with a low noise level can be efficiently designed.
The above object can also be fulfilled by a design aiding apparatus for aiding division of each plane into subplanes in a multilayer circuit board which includes at least one plane that is one of a power plane and a ground plane and at least one signal layer on which a plurality of circuit blocks are placed, the design aiding apparatus including: a circuit block judging unit for classifying each of the plurality of circuit blocks under a first type of a circuit block that contains a predetermined signal line over which a specific signal flows and a second type of a circuit block aside from the first type, the specific signal being a signal whose amount of change in a fixed period of time is no less than a predetermined value; and a slit forming unit for dividing each plane into at least two subplanes and calculating coordinates of a slit that is a non-conductor area present between each adjacent two of the subplanes, wherein each of the subplanes corresponds to one of an integrated placement area of circuit blocks of the first type and an integrated placement area of circuit blocks of the second type.
With this construction, slits which correspond to boundary lines between high-speed circuit blocks and other circuit blocks on a signal layer are formed on each plane, so that leakage of common-mode currents from the high-speed circuit blocks to the other circuit blocks will be prevented. Accordingly, a circuit board of a low noise level can efficiently be designed.
The above object can also be fulfilled by a design aiding apparatus for aiding division of each plane into subplanes in a multilayer circuit board which includes at least one plane that is one of a power plane and a ground plane and at least one signal layer on which a plurality of circuit blocks are placed, the design aiding apparatus including: a circuit block judging unit for classifying each of the plurality of circuit blocks under a first type of a circuit block that contains a predetermined signal line over which a specific signal flows and a second type of a circuit block aside from the first type, the specific signal being a signal whose amount of change in a fixed period of time is no less than a predetermined value; a circuit block combining unit for combining placement areas of circuit blocks of a same type into one integrated placement area and as a result generating at least one integrated placement area on the signal layer; and a subplane generating unit for dividing each plane into at least two subplanes and calculating coordinates of a slit that is a non-conductor area present between each adjacent two of the subplanes, wherein each of the subplanes corresponds to one of the integrated placement areas generated by the circuit block combining unit.
With this construction, each plane is divided into subplanes which correspond to an integrated placement area of the high-speed circuit blocks and an integrated placement area of the other circuit blocks after components of each circuit block is placed on a signal layer, so that leakage of common-mode currents from the high-speed circuit blocks to the other circuit blocks will be prevented. Accordingly, a circuit board with a low noise level can efficiently be designed.
The above object can also be fulfilled by a design aiding apparatus for aiding division of each plane into subplanes in a multilayer circuit board which includes at least one plane that is one of a power plane and a ground plane and at least one signal layer on which a plurality of circuit blocks are placed, wherein at least one conductor is placed as a signal line in each of the plurality of circuit blocks, the design aiding apparatus including: a storing unit for storing, for each signal line, at least one of a frequency and a transition time of a signal that flows over the signal line; a circuit block judging unit for reading, for each of the plurality of circuit blocks, at least one of a frequency and a transition time of a signal that flows over a signal line contained in the circuit block from the storing unit, and judging whether the circuit block is a circuit block of a first type which contains a predetermined signal line over which a specific signal flows or a circuit block of a second type aside from the first type, the specific signal being a signal that has any of a frequency no less than a predetermined frequency and a transition time no more than a predetermined transition time; a circuit block combining unit for combining placement areas of circuit blocks of a same type into one integrated placement area and as a result generating at least one integrated placement area on the signal layer; a subplane generating unit for dividing each plane into at least two subplanes that correspond to the integrated placement areas generated by the circuit block combining unit, and calculating coordinates of a slit that is a non-conductor area present between each adjacent two of the subplanes; an intersection judging unit for judging whether an area, formed by projecting a conductor placement area of a conductor of each predetermined signal line onto each plane, intersects a slit present on each plane; a plane judging unit for judging, when the intersection judging unit judges that the area intersects the slit, whether two subplanes which sandwich the slit have been generated from a same plane; and a conductor adding unit for calculating a conductor placement area in the area to place a conductor which connects the two subplanes when the plane judging unit judges that the two subplanes have been generated from the same plane.
With this construction, a feedback path of a current that flows over a predetermined signal line such as a high-speed signal line is secured in a slit between two subplanes generated from the same plane, so that a circuit board with a low noise level can be designed. Also, since a conductor is used to connect the two subplanes, the two subplanes can be treated as a single net.
The above object can also be fulfilled by a design aiding apparatus for aiding division of each plane into subplanes in a multilayer circuit board which includes at least one plane that is one of a power plane and a ground plane and at least one signal layer on which a plurality of circuit blocks are placed, wherein at least one conductor is placed as a signal line in each of the plurality of circuit blocks, the design aiding apparatus including: a storing unit for storing, for each signal line, at least one of a frequency and a transition time of a signal that flows over the signal line; a circuit block judging unit for reading, for each of the plurality of circuit blocks, at least one of a frequency and a transition time of a signal that flows over a signal line contained in the circuit block from the storing unit, and judging whether the circuit block is a circuit block of a first type which contains a predetermined signal line over which a specific signal flows or a circuit block of a second type aside from the first type, the specific signal being a signal that has any of a frequency no less than a predetermined frequency and a transition time no more than a predetermined transition time; a circuit block combining unit for combining placement areas of circuit blocks of a same type into one integrated placement area and as a result generating at least one integrated placement area on the signal layer; a subplane generating unit for dividing each plane into at least two subplanes that correspond to the integrated placement areas generated by the circuit block combining unit, and calculating coordinates of a slit that is a non-conductor area present between each adjacent two of the subplanes; an intersection judging unit for judging whether an area, formed by projecting a conductor placement area of a conductor of each predetermined signal line onto each plane, intersects a slit present on each plane; a plane judging unit for judging, when the intersection judging unit judges that the area intersects the slit, whether two subplanes which sandwich the slit have been generated from a same plane; a potential judging unit for judging, when the plane judging unit judges that the two subplanes have been generated from different planes, whether the two subplanes have a same potential; and a jumper adding unit for calculating a placement position in the area for a jumper which connects the two subplanes, when the potential judging unit judges that the two subplanes have the same potential.
With this construction, a feedback path of a current that flows over a predetermined signal line such as a high-speed signal line is secured in a slit between two subplanes which have been generated from different planes but which have the same potential. Accordingly, a circuit board with a low noise level can be designed with efficiency. Also, since a jumper is used to connect the two subplanes that belong to different nets, it is possible to prevent shorts in the nets.
The above object can also be fulfilled by a design aiding apparatus for aiding division of each plane into subplanes in a multilayer circuit board which includes at least one plane that is one of a power plane and a ground plane and at least one signal layer on which a plurality of circuit blocks are placed, wherein at least one conductor is placed as a signal line in each of the plurality of circuit blocks, the design aiding apparatus including: a storing unit for storing, for each signal line, at least one of a frequency and a transition time of a signal that flows over the signal line; a circuit block judging unit for reading, for each of the plurality of circuit blocks, at least one of a frequency and a transition time of a signal that flows over a signal line contained in the circuit block from the storing unit, and judging whether the circuit block is a circuit block of a first type that contains a predetermined signal line over which a specific signal flows or a circuit block of a second type aside from the first type, the specific signal being a signal that has any of a frequency no less than a predetermined frequency and a transition time no more than a predetermined transition time; a circuit block combining unit for combining placement areas of circuit blocks of a same type into one integrated placement area and as a result generating at least one integrated placement area on the signal layer; a subplane generating unit for dividing each plane into at least two subplanes that correspond to the integrated placement areas generated by the circuit block combining unit, and calculating coordinates of a slit that is a non-conductor area present between each adjacent two of the subplanes; an intersection judging unit for judging whether an area, formed by projecting a conductor placement area of a conductor of each predetermined signal line onto each plane, intersects a slit present on each plane; a plane judging unit for judging, when the intersection judging unit judges that the area intersects the slit, whether two subplanes which sandwich the slit have been generated from a same plane; a potential judging unit for judging, when the plane judging unit judges that the two subplanes have been generated from different planes, whether the two subplanes have a same potential; and a capacitor element adding unit for calculating a placement position in the area for a capacitor element which connects the two subplanes, when the potential judging unit judges that the two subplanes have different potentials.
With this construction, only by adding a capacitor element in a slit between two subplanes of different potentials, a feedback path of a current that flows over a predetermined signal line can be secured, with it being possible to reduce noise in designing a circuit board.